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september 2011 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator fan5400 / fan5401 / FAN5402 / fan5403 / fan5404 / fan5405 usb-compliant single-cell li -ion switching charger with usb-otg boost regulator features ? fully integrated, high-efficiency charger for single-cell li-ion and li-polymer battery packs ? faster charging than linear ? charge voltage accuracy: ? 0.5% at 25c ? 1% from 0 to 125c ? ? 5% input current re gulation accuracy ? ? 5% charge current regulation accuracy ? 20v absolute maximum input voltage ? 6v maximum input operating voltage ? 1.25a maximum charge rate ? programmable through high-speed i 2 c interface (3.4mb/s) with fast mode plus compatibility ? input current ? fast-charge / termination current ? charger voltage ? termination enable ? 3mhz synchronous buck pwm controller with wide duty cycle range ? small footprint 1 ? h external inductor ? safety timer with reset control ? 1.8v regulated output from vbus for auxiliary circuits ? weak input sources accommodated by reducing charging current to maintain minimum vbus voltage ? low reverse leakage to prevent battery drain to vbus ? 5v, 300ma boost mode for usb otg for 2.5 to 4.5v battery input applications ? cell phones, smart phones, pdas ? tablet, portable media players ? gaming device, digital cameras description the fan5400 family (fan540x) combines a highly integrated switch-mode charger, to minimi ze single-cell lithium-ion (li-ion) charging time from a usb power source, and a boost regulator to power a usb peripheral from the battery. the charging parameters and operating modes are programmable through an i 2 c interface that operates up to 3.4mbps. the charger and boost re gulator circuits switch at 3mhz to minimize the size of external passive components. the fan540x provides battery charging in three phases: conditioning, constant curre nt, and constant voltage. to ensure usb compliance and minimize charging time, the input current is limited to the value set through the i 2 c host. charge termination is determined by a programmable minimum current level. a safe ty timer with reset control provides a safety backup for the i 2 c host. the integrated circuit (ic) automatically restarts the charge cycle when the battery falls below an internal threshold. if the input source is removed, the ic enters a high-impedance mode with leakage from the battery to the input prevented. charge status is reported ba ck to the host through the i 2 c port. charge current is reduced when the die temperature reaches 120c. the fan540x can operate as a boost regulator on command from the system. the boost regulator includes a soft-start that limits inrush current from the battery. the fan540x is available in a 1.96 x 1.87mm, 20-bump, 0.4mm pitch wlcsp package. fan540x sw pgnd c out l1 vbat + battery csin r sense 68m ? 1 ? h c bat system load 0.1 ? f vbus 1 ? f pmid 4.7 ? f sda scl otg/usb# c reg 1 ? f vreg stat 10 ? f disable c bus c mid figure 1. typical application (fan5403-05 pin out) a ll trademarks are the p ro p ert y of their res p ective owners. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 2 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator ordering information part number temperature range package pn bits: ic_info[4:3] packing method fan5400ucx -40 to 85c 20- bump, wafer- level chip-scale package (wlcsp), 0.4mm pitch, estimated size: 1.96 x 1.87mm 01 tape and reel fan5401ucx -40 to 85c 00 tape and reel FAN5402ucx -40 to 85c 01 tape and reel fan5403ucx -40 to 85c 10 tape and reel fan5404ucx -40 to 85c 11 tape and reel fan5405ucx -40 to 85c 10 tape and reel table 1. feature comparison summary part number pn bits: reg3[4:3] slave address automatic charge special charger (1) safety limits battery absent behavior e2 pin vreg (e3 pin) fan5400 01 1101011 yes no no off auxpwr (connect to vbat) pmid fan5401 00 1101011 no no no off FAN5402 01 1101011 yes no no on fan5403 10 1101011 yes yes yes off disable 1.8v fan5404 11 1101011 no yes yes off fan5405 10 1101010 yes yes yes on note: 1. special charger is a current limited c harger that is not a usb compliant source. table 2. recommended external components component description vendor parameter typ. unit l1 1 ? h, 20%, 1.3a, 2016 murata: lqm2mpn1r0m or equivalent l 1.0 ? h dcr (series r) 85 m ? c bat 10 ? f, 20%, 6.3v, x5r, 0603 murata: grm188r60j106m tdk: c1608x5r0j106m c 10 ? f c mid 4.7 ? f, 10%, 6.3v, x5r, 0603 murata: grm188r60j475k tdk: c1608x5r0j475k c (2) 4.7 ? f c bus 1.0 ? f, 10%, 25v, x5r, 0603 murata grm188r61e105k tdk:c1608x5r1e105m c 1.0 ? f note: 2. 6.3v rating is sufficient for c mid since pmid is protected from over-voltage surges on vbus by q3 (figure 3). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 3 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator block diagram figure 2. ic and system block diagram q2 pmid c in2 vbus c in1 q1 q1b sw pgnd l1 vbat 1 ? h c out + battery r sense 68m ? c bat system load q3 q1a charge pump csin figure 3. power stage pmid q1 a q1b greater than vbat on off less than vbat off on www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 4 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator pin configuration c1 b1 a1 a2 c3 b3 a3 c2 d1 d3 d2 b2 c4 b4 a4 d4 e1 e3 e2 e4 top view c1 b1 a1 c3 b3 a3 a2 c2 d1 d3 d2 b2 c4 b4 a4 d4 e1 e3 e2 e4 bottom view figure 4. wlcsp-20 pin assignments pin definitions pin # name part # description a1, a2 vbus all charger input voltage and usb-otg output voltage. bypass with a 1 ? f capacitor to pgnd. a3 nc all no connect . no external connection is made between this pin and the ic?s internal circuitry. a4 scl all i 2 c interface serial clock . this pin should not be left floating. b1-b3 pmid all power input voltage . power input to the charger regulator, bypass point for the input current sense, and high-voltage input switch. bypass with a minimum of 4.7 ? f, 6.3v capacitor to pgnd. b4 sda all i 2 c interface serial data . this pin should not be left floating. c1-c3 sw all switching node . connect to output inductor. c4 stat all status . open-drain output indicating charge status . the ic pulls this pin low when charge is in process. d1-d3 pgnd all power ground . power return for gate drive and power transistors. the connection from this pin to the bottom of c mid should be as short as possible. d4 otg all on-the-go . enables boost regulator in conjunction with otg_en and otg_pl bits (see table 16) . on vbus power-on reset (por), this pin sets the input current limit for t 15min charging. e1 csin all current-sense input . connect to the sense resistor in series with the battery. the ic uses this node to sense current into the battery. bypass this pin with a 0.1 ? f capacitor to pgnd. e2 auxpwr fan5400, fan5401, FAN5402 auxiliary power . connect to the battery pack to provide ic power during high-impedance mode. bypass with a 1 ? f capacitor to pgnd. e2 disable fan5403, fan5404, fan5405 charge disable . if this pin is high, charging is disabled. when low, charging is controlled by the i 2 c registers. when this pin is high, the 15-minute timer is reset. this pin does not affect the 32-second timer. e3 vreg all regulator output . connect to a 1 ? f capacitor to pgnd. this pin can supply up to 2ma of dc load current. for fan5400-FAN5402, the out put voltage is pmid, which is limited to 6.5v. for fan5403-fan5405, the out put voltage is regulated to 1.8v. e4 vbat all battery voltage . connect to the positive (+) terminal of the battery pack. bypass with a 0.1 ? f capacitor to pgnd if the battery is connected through long leads. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 5 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating condit ions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v bus vbus voltage continuous ?1.4 20.0 v pulsed, 100ms maximum non-repetitive ?2.0 v stat stat voltage ?0.3 16.0 v v i pmid voltage 7.0 v sw, csin, vbat, auxpwr, disable voltage ?0.3 7.0 v o voltage on other pins ?0.3 6.5 (3) v dt dv bus maximum vbus slope above 5.5v when boost or charger are active 4 v/ ? s esd electrostatic discharge protection level human body model per jesd22-a114 2000 v charged device model per jesd22-c101 500 t j junction temperature ?40 +150 c t stg storage temperature ?65 +150 c t l lead soldering temperature, 10 seconds +260 c note: 3. lesser of 6.5v or v i + 0.3v. recommended operating conditions the recommended operating conditions t able defines the conditions for actual device operation. recommended operating conditions are specified to ensure opt imal performance to the datasheet specif ications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. units v bus supply voltage 4 6 v v bat(max) maximum battery voltage when boost enabled 4.5 v dt dv bus ? negative vbus slew rate du ring vbus short circuit, c mid < 4.7 ? f, see vbus short while charging t a < 60c 4 v/ ? s t a > 60c 2 t a ambient temperature ?30 +85 c t j junction temperature (see thermal regulation and protection section) ?30 +120 c thermal properties junction-to-ambient thermal resistance is a function of application and board layout. this data is measured with four-layer 2s2p boards in accordance to jedec standard jesd51. special a ttention must be paid not to exceed junction temperature t j(max) at a given ambient temperature t a . for measured data, see table 11. symbol parameter typical units ? ja junction-to-ambient thermal resistance 60 c/w ? jb junction-to-pcb thermal resistance 20 c/w www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 6 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator electrical specifications unless otherwise specified: according to the circuit of figure 1; recommended operating temperature range for t j and t a ; v bus =5.0v; hz_mode; opa_mode=0; (charge mode); scl, sd a, otg=0 or 1.8v; and typical values are for t j =25c. symbol parameter conditions min. typ. max. units power supplies i vbus vbus current v bus > v bus(min) , pwm switching 10 ma v bus > v bus(min) ; pwm enabled, not switching (battery ovp condition); i_in setting=100ma 2.5 ma 0c < t j < 85c, hz_mode=1 v bat < v lowv , 32s mode 63 90 ? a i lkg vbat to vbus leakage current 0c < t j < 85c, hz_mode=1, v bat =4.2v, v bus =0v 0.2 5.0 ? a i bat battery discharge current in high- impedance mode 0c < t j < 85c, hz_mode=1, v bat =4.2v 20 ? a fan5403-05, disable=1, 0c < t j < 85c, v bat =4.2v 10 charger voltage regulation v oreg charge voltage range 3.5 4.4 v charge voltage accuracy t a =25c ?0.5% +0.5% t j =0 to 125c ?1% +1% charging current regulation i ochrg output charge current range v lowv < v bat < v oreg v bus > v slp , r sense =68m ? 550 1250 ma charge current accuracy across r sense 20mv < v ireg < 40mv fan5400-02 95 100 105 % fan5403-05 92 97 102 v ireg > 40mv fan5400-02 97 100 103 fan5403-05 94 97 100 weak battery detection v lowv weak battery threshold range 3.4 3.7 v weak battery threshold accuracy ?5 +5 % weak battery deglitch time rising voltage, 2mv overdrive 30 ms logic levels: disable, sda, scl, otg v ih high-level input voltage 1.05 v v il low-level input voltage 0.4 v i in input bias current input tied to gnd or v in 0.01 1.00 ? a charge termination detection i (term) termination current range v bat > v oreg ? v rch , v bus > v slp , r sense =68m ? 50 400 ma termination current accuracy [v csin ? v bat ] from 3mv to 20mv ?25 +25 % [v csin ? v bat ] from 20mv to 40mv ?5 +5 termination current deglitch time 2mv overdrive 30 ms 1.8v linear regulator v reg 1.8v regulator output i reg from 0 to 2ma, fan5403-05 1.7 1.8 1.9 v continued on the following page? www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 7 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator electrical specifications unless otherwise specified: according to the circuit of figure 1; recommended operating temperature range for t j and t a ; v bus =5.0v; hz_mode; opa_mode=0; (charge mode); scl, sd a, otg=0 or 1.8v; and typical values are for t j =25c. symbol parameter conditions min. typ. max. units input power source detection v in(min)1 vbus input voltage rising to initiate and pass vbus validation 4.29 4.42 v v in(min)2 minimum vbus during charge during charging 3.71 3.94 v t vbus_valid vbus validation time 30 ms special charger (v bus ) (fan5403 ? fan5405) v sp special charger setpoint accuracy ?3 +3 % input current limit i inlim input current limit threshold i in set to 100ma 88 93 98 ma i in set to 500ma 450 475 500 v ref bias generator v ref bias regulator voltage v bus > v in(min) or v bat > v bat(min) 6.5 v short-circuit current limit 20 ma battery recharge threshold v rch recharge threshold below v (oreg) 100 120 150 mv ? deglitch time v bat falling below v rch threshold 130 ms stat output v stat(ol) stat output low i stat =10ma 0.4 v ? i stat(oh) stat high leakage current v stat =5v 1 ? a ? battery detection i detect battery detection current before charge done (sink current) (4) begins after termination detected and v bat < v oreg ?v rch ?0.80 ma t detect battery detection time 262 ms sleep comparator v slp sleep-mode entry threshold, v bus ? v bat 2.3v < v bat < v oreg , v bus falling 0 0.04 0.10 v v slp_exit deglitch time for vbus rising above v slp + v slp_exit rising voltage 30 ms power switches (see figure 3) r ds(on) q3 on resistance (vbus to pmid) i in(limit) =500ma 180 250 m ? ? q1 on resistance (pmid to sw) 130 225 q2 on resistance (sw to gnd) 150 225 charger pwm modulator f sw oscillator frequency 2.7 3.0 3.3 mhz d max maximum duty cycle 100 % d min minimum duty cycle 0 % i sync synchronous to non-synchronous current cut-off threshold (5) low-side mosfet (q2) cycle-by- cycle current limit 140 ma continued on the following page? www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 8 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator electrical specifications unless otherwise specified: according to the circuit of figure 1; recommended operating temperature range for t j and t a ; v bus =5.0v; hz_mode; opa_mode=0; (charge mode); scl, sd a, otg=0 or 1.8v; and typical values are for t j =25c. symbol parameter conditions min. typ. max. units boost mode operation (opa_mode=1, hz_mode=0) v boost boost output voltage at vbus 2.5v < v bat < 4.5v, i load from 0 to 200ma 4.80 5.07 5.17 v 2.7v < v bat < 4.5v, i load from 0 to 200ma 4.85 5.07 5.17 i bat(boost) boost mode quiescent current pfm mode, v bat =3.6v, i out =0 140 300 ? a i limpk(bst) q2 peak current limit 1100 1380 1660 ma ? uvlo bst minimum battery voltage for boost operation while boost active 2.42 v to start boost regulator 2.58 2.70 vbus load resistance r vbus vbus to pgnd resistance normal operation 1500 k ? charger validation 100 ? protection and timers vbus ovp vbus over-voltage shutdown v bus rising 6.09 6.29 6.49 v hysteresis v bus falling 100 mv i limpk(chg) q1 cycle-by-cycle peak current limit charge mode 2.3 a ? v short battery short-circu it threshold v bat rising 1.95 2.00 2.05 v hysteresis v bat falling 100 i short linear charging current v bat < v short 20 30 40 ma t shutdwn thermal shutdown threshold (6) t j rising 145 c hysteresis (6) t j falling 10 t cf thermal regulation threshold (6) charge current reduction begins 120 c t int detection interval 2.1 s t 32s 32-second timer (7) charger enabled 20.5 25.2 28.0 s charger disabled 18.0 25.2 34.0 t 15min 15-minute timer 15-minute mode (fan5400, FAN5402, fan5404, fan5405) 12.0 13.5 15.0 min ? t lf low-frequency timer accuracy charger inactive ?25 25 % notes: 4. negative current is current flowing from the battery to v bus (discharging the battery). 5. q2 always turns on for 60ns, then turns off if current is below i sync . 6. guaranteed by design; not tested in production. 7. this tolerance (%) applies to all timers on the ic, including soft-start and deglitching timers. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 9 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator i 2 c timing specifications guaranteed by design. symbol parameter conditions min. typ. max. units f scl scl clock frequency standard mode 100 khz fast mode 400 high-speed mode, c b < 100pf 3400 high-speed mode, c b < 400pf 1700 t buf bus-free time between stop and start conditions standard mode 4.7 ? s fast mode 1.3 t hd;sta start or repeated start hold time standard mode 4 ? s fast mode 600 ns high-speed mode 160 ns t low scl low period standard mode 4.7 ? s fast mode 1.3 ? s high-speed mode, c b < 100pf 160 ns high-speed mode, c b < 400pf 320 ns t high scl high period standard mode 4 ? s fast mode 600 ns high-speed mode, c b < 100pf 60 ns high-speed mode, c b < 400pf 120 ns t su;sta repeated start setup time standard mode 4.7 ? s fast mode 600 ns high-speed mode 160 ns t su;dat data setup time standard mode 250 ns fast mode 100 high-speed mode 10 t hd;dat data hold time standard mode 0 3.45 ? s fast mode 0 900 ns high-speed mode, c b < 100pf 0 70 ns high-speed mode, c b < 400pf 0 150 ns t rcl scl rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 high-speed mode, c b < 100pf 10 80 high-speed mode, c b < 400pf 20 160 t fcl scl fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 high-speed mode, c b < 100pf 10 40 high-speed mode, c b < 400pf 20 80 t rda t rcl1 sda rise time rise time of scl after a repeated start condition and after ack bit standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 high-speed mode, c b < 100pf 10 80 high-speed mode, c b < 400pf 20 160 continued on the following page? www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 10 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator i 2 c timing specifications guaranteed by design. symbol parameter conditions min. typ. max. units t fda sda fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 high-speed mode, c b < 100pf 10 80 high-speed mode, c b < 400pf 20 160 t su;sto stop condition setup time standard mode 4 ? s fast mode 600 ns high-speed mode 160 ns c b capacitive load for sda, scl 400 pf timing diagrams start repeated start scl sda t f t hd;sta t low t r t hd;dat t high t su;dat t su;sta t hd;sto t buf start stop t hd;sta figure 5. i 2 c interface timing for fast and slow modes repeated start sclh sdah t fda t low t rcl1 t hd;dat t high t su;sto repeated start t rda t fcl t su;dat t rcl stop = mcs current source pull-up = r p resistor pull-up note a note a: first rising edge of sclh afte r repeated start and after each ack bit. t hd;sta t su;sta figure 6. i 2 c interface timing for high-speed mode www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 11 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator charge mode typical characteristics unless otherwise specified, circuit of figure 1, v oreg =4.2v, v bus =5.0v, and t a =25c. - 20 40 60 80 100 120 140 160 180 2.5 3 3.5 4 4.5 battery charge current (ma) battery voltage, v bat (v) 5.5vbus 5.0vbus 4.5vbus - 100 200 300 400 500 600 700 800 900 2.5 3 3.5 4 4.5 battery charge current (ma) battery voltage, v bat (v) 5.5vbus 5.0vbus 4.5vbus figure 7. battery charge current vs. v bus with i inlim =100ma figure 8. battery charge current vs. v bus with i inlim =500ma 84% 86% 88% 90% 92% 94% 550 650 750 850 950 1050 1150 1250 efficiency v bat load current (ma) 4.20vbat, 4.5vbus 4.20vbat, 5.0vbus 3.54vbat, 5.0vbus 3.54vbat, 4.5vbus 84% 86% 88% 90% 92% 94% 2.52.72.93.13.33.53.73.94.14.3 efficiency battery voltage, v bat (v) 4.5vbus 5.0vbus 5.5vbus figure 9. charger efficiency, no i inlim , i ocharge =1,250ma figure 10. charger efficiency vs. v bus , i inlim =500ma figure 11. auto-charge startup at v bus plug-in, i inlim =100ma, otg=1, v bat =3.4v figure 12. auto-charge startup at v bus plug-in, i inlim =500ma, otg=1, v bat =3.4v www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 12 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator charge mode typical characteristics unless otherwise specified, circuit of figure 1, v oreg =4.2v, v bus =5.0v, and t a =25c. figure 13. autocharge startup with 300ma limited charger / adaptor, i inlim =500ma, otg=1, v bat =3.4v figure 14. charger startup with hz_mode bit reset, i inlim =500ma, i ocharge =950ma, oreg=4.2v, v bat =3.6v figure 15. battery removal / insertion during charging, v bat =3.9v, i ocharge =950ma, no i inlim, te=0 figure 16. battery removal / insertion during charging, v bat =3.9v, i ocharge =950ma, no i inlim, te=1 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 13 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator charge mode typical characteristics unless otherwise specified, circuit of figure 1, v oreg =4.2v, v bus =5.0v, and t a =25c. figure 17. no battery at v bus power-up; fan5400, fan5403 figure 18. no battery at v bus power-up; FAN5402, fan5405 0 50 100 150 200 4.0 4.5 5.0 5.5 6.0 high-z mode current ( ? a) input voltage, v bus (v) -30c +25c +85c 1.77 1.78 1.79 1.80 1.81 1.82 012345 v reg (v) 1.8v regulator load current (ma) -10c, 5.0vbus +25c, 5.0vbus +85c, 5.0vbus figure 19. vbus current in high-impedance mode with battery open figure 20. v reg 1.8v output regulation www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 14 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator boost mode typical characteristics unless otherwise specified, using circuit of figure 1, v bat =3.6v, t a =25c. 75 80 85 90 95 100 0 50 100 150 200 250 300 efficiency (%) v bus load current (ma) 2.7vbat 3.6vbat 4.2vbat 75 80 85 90 95 100 0 50 100 150 200 250 300 efficiency (%) v bus load current (ma) -10c, 3.6vbat +25c, 3.6vbat +85c, 3.6vbat figure 21. efficiency vs. v bat figure 22. efficiency over temperature 4.94 4.97 5.00 5.03 5.06 5.09 5.12 0 50 100 150 200 250 300 v bus (v) v bus load current (ma) 2.7vbat 3.6vbat 4.2vbat 4.94 4.97 5.00 5.03 5.06 5.09 5.12 0 50 100 150 200 250 300 v bus (v) v bus load current (ma) -10c, 3.6vbat +25c, 3.6vbat +85c, 3.6vbat figure 23. output regulation vs. v bat figure 24. output regulation over temperature 50 100 150 200 250 22.533.544.55 quiescent current (a) battery voltage, v bat (v) -30c +25c +85c 0 5 10 15 20 22.533.544.55 high-z mode current (a) battery voltage, v bat (v) -30c +25c +85c figure 25. quiescent current figure 26. high-impedance mode battery current www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 15 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator boost mode typical characteristics unless otherwise specified, using circuit of figure 1, v bat =3.6v, t a =25c. figure 27. boost pwm waveform figure 28. boost pfm waveform 0 5 10 15 20 25 30 0 50 100 150 200 250 300 v bus ripple (mv pp ) v bus load current (ma) 2.7vbat 3.6vbat 4.2vbat 4.5vbat 0 5 10 15 20 25 30 0 50 100 150 200 250 300 v bus ripple (mv pp ) v bus load current (ma) -30c, 3.6vbat +25c, 3.6vbat +85c, 3.6vbat figure 29. output ripple vs. v bat figure 30. output ripple vs. temperature www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 16 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator boost mode typical characteristics unless otherwise specified, using circuit of figure 1, v bat =3.6v, t a =25c. figure 31. startup, 3.6v bat , 44 ? load, additional 10f, x5r across v bus figure 32. v bus fault response, 3.6v bat figure 33. load transient, 5-155-5ma, t r =t f =100ns figure 34. load transient, 5-255-5ma, t r =t f =100ns www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 17 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator circuit description / overview when charging batteries with a current-limited input source, such as usb, a switching charger?s high efficiency over a wide range of output voltages minimizes charging time. fan540x combines a highly integrated synchronous buck regulator for charging with a synchronous boost regulator, which can supply 5v to usb on-the-go (otg) peripherals. the regulator employs synchronous rectification for both the charger and boost regulators to maintain high efficiency over a wide range of battery voltages and charge states. the fan540x has three operating modes: 1. charge mode: charges a single-cell li-ion or li-polymer battery. 2. boost mode: provides 5v power to usb-otg with an integrated synchronous rectification boost regulator using the battery as input. 3. high-impedance mode: both the boost and charging circuits are off in this mode. current flow from vbus to the battery or from the battery to vbus is blocked in this mode. this mode consumes very little current from vbus or the battery. note: default settings are denoted by bold typeface . charge mode in charge mode, fan540x employs four regulation loops: 1. input current: limits the amount of current drawn from vbus. this current is sensed internally and can be programmed through the i 2 c interface. 2. charging current: limits the maximum charging current. this current is sensed using an external r sense resistor. 3. charge voltage: the regulator is restricted from exceeding this voltage. as the internal battery voltage rises, the battery?s internal impedance and r sense work in conjunction with the charge voltage regulation to decrease the amount of curr ent flowing to the battery. battery charging is completed when the voltage across r sense drops below the i term threshold. 4. temperature: if the ic?s junction temperature reaches 120c, charge current is cont inuously reduced until the ic?s temperature stabilizes at 120c. in addition, the fan5403-05 employ an additional loop to limit the amount of drop on vb us to a programmable voltage (v sp ) to accommodate ?special chargers? that limit current to a lower current than might be available from a ?normal? usb wall charger. battery charging curve if the battery voltage is below v short , a linear current source pre-charges the battery until v bat reaches v short . the pwm charging circuit is then started and the battery is charged with a constant current if sufficient input power is available. the current slew rate is limited to prevent overshoot. the fan540x is designed to work with a current-limited input source at vbus. during the current regulation phase of charging, i inlim or the programmed char ging current limits the amount of current available to charge the battery and power the system. the effect of i inlim on i charge can be seen in figure 36. v oreg v b a t i short i charge pre- charge current regulation voltage regulation i ocharge v short i term figure 35. charge curve, i charge not limited by i inlim v oreg i short i c h a r g e pre- charge current regulation voltage regulation v short i term v b a t figure 36. charge curve, i inlim limits i charge assuming that v oreg is programmed to the cell?s fully charged ?float? voltage, the curr ent that the battery accepts with the pwm regulator limiting its output (sensed at vbat) to v oreg declines, and the charger enters the voltage regulation phase of charging . when the current declines to the programmed i term value, the charge cycle is complete. charge current termination can be disabled by resetting the te bit (reg1[3]). the charger output or ?float? voltage can be programmed by the oreg bits from 3.5v to 4.44v in 20mv increments, as shown in table 3. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 18 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator table 3. oreg bits (oreg[7:2]) vs. charger v out (v oreg ) float voltage decimal hex voreg decimal hex voreg 0 00 3.50 32 20 4.14 1 01 3.52 33 21 4.16 2 02 3.54 34 22 4.18 3 03 3.56 35 23 4.20 4 04 3.58 36 24 4.22 5 05 3.60 37 25 4.24 6 06 3.62 38 26 4.26 7 07 3.64 39 27 4.28 8 08 3.66 40 28 4.30 9 09 3.68 41 29 4.32 10 0a 3.70 42 2a 4.34 11 0b 3.72 43 2b 4.36 12 0c 3.74 44 2c 4.38 13 0d 3.76 45 2d 4.40 14 0e 3.78 46 2e 4.42 15 0f 3.80 47 2f 4.44 16 10 3.82 48 30 4.44 17 11 3.84 49 31 4.44 18 12 3.86 50 32 4.44 19 13 3.88 51 33 4.44 20 14 3.90 52 34 4.44 21 15 3.92 53 35 4.44 22 16 3.94 54 36 4.44 23 17 3.96 55 37 4.44 24 18 3.98 56 38 4.44 25 19 4.00 57 39 4.44 26 1a 4.02 58 3a 4.44 27 1b 4.04 59 3b 4.44 28 1c 4.06 60 3c 4.44 29 1d 4.08 61 3d 4.44 30 1e 4.10 62 3e 4.44 the following charging parameters can be programmed by the host through i 2 c: table 4. programmable charging parameters parameter name register output voltage regulation v oreg reg2[7:2] battery charging current limit i ochrg reg4[6:4] input current limit i inlim reg1[7:6] charge termination limit i term reg4[2:0] weak battery voltage v lowv reg1[5:4] a new charge cycle begins when one of the following occurs: ? the battery voltage falls below v oreg - v rch ? vbus power on reset (por) clears and the battery voltage is below the weak battery threshold (v lowv ). this occurs for all versions except the fan5401. ? ce or hz_mode is reset through i 2 c write to control1 (r1) register. charge current limit (i ocharge ) table 5. i ocharge (reg4 [6:4]) current as function of i ocharge bits and r sense resistor values dec bin hex v rsense (mv) i ocharge (ma) 68m ? 100m ? 0 000 00 37.4 550 374 1 001 01 44.2 650 442 2 010 02 51.0 750 510 3 011 03 57.8 850 578 4 100 04 64.6 950 646 5 101 05 71.4 1050 714 6 110 06 78.2 1150 782 7 111 07 85.0 1250 850 termination current limit current charge termination is enabled when te (reg1[3])=1. typical termination current values are given in table 6. table 6. i term current as function of i term bits (reg4[2:0]) and r sense resistor values fan5400 - FAN5402 fan5403 - fan5405 i term v rsense (mv) i term (ma) v rsense (mv) i term (ma) 68m ? 100m ? 68m ? 100m ? 0 3.4 50 34 3.3 49 33 1 6.8 100 68 6.6 97 66 2 10.2 150 102 9.9 146 99 3 13.6 200 136 13.2 194 132 4 17.0 250 170 16.5 243 165 5 20.4 300 204 19.8 291 198 6 23.8 350 238 23.1 340 231 7 27.2 400 272 26.4 388 264 when the charge current falls below i term , pwm charging stops and the stat bits change to ready (00) for about 500ms while the ic determines whether the battery and charging source are still connec ted. stat then changes to charge done (10), provided the battery and charger are still connected. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 19 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator pwm controller in charge mode the ic uses a current-mode pwm controller to regulate the output voltage and battery charge currents. the synchronous rectifier (q2) has a negative curr ent limit that turns off q2 at 140ma to prevent current flow from the battery. safety timer this section references figure 41 and figure 42. at the beginning of charging, t he ic starts a 15-minute timer (t 15min ). when this timer times out, charging is terminated. writing to any register through i 2 c stops and resets the t 15min timer, which in turn starts a 32-second timer (t 32s ). setting the tmr_rst bit (reg0[7]) resets the t 32s timer. if the t 32s timer times out, charging is terminated, the registers are set to their default values, and charging resumes using the default values with the t 15min timer running. normal charging is controlled by the host with the t 32s timer running to ensure that the host is alive. charging with the t 15min timer running is used for charging that is unattended by the host. if the t 15min timer expires, the ic turns off the charger, sets the ce bit, and indicates a timer fault (110) on the fault bits (reg0[2:0] ). this sequence prevents overcharge if the host fails to reset the t 32s timer. v bus por / non-compliant charger rejection when the ic detects that v bus has risen above v in(min)1 (4.4v), the ic applies a 110 ? load from vbus to gnd. to clear the vbus por (power-on-reset) and begin charging, vbus must remain above v in(min)1 and below vbus ovp for t vbus_valid (30ms) before the ic initiates charging. the vbus validation sequence always occurs before charging is initiated or re-initiated (for example, after a vbus ovp fault or a v rch recharge initiation). t vbus_valid ensures that unfiltered 50/60hz chargers and other non-compliant chargers are rejected. usb-friendly boot sequence for all versions except fan5401, fan5404 at vbus por, when the battery voltage is above the weak battery threshold (v lowv ), the ic operates in accordance with its i 2 c register settings. if v bat < v lowv , the ic sets all registers to their default values and enables the charger using an input current limit controlled by the otg pin (100ma if otg is low and 500ma if otg is high). this feature can revive a battery whose voltage is too low to ensure reliable host operation. charging continues in the absence of host communication even after the battery has reached v oreg , whose default value is 3.54v, and the charger remains active until t 15min times out. once the host processor begins writing to the ic, charging parameters are set by the host, which must continually reset the t 32s timer to continue charging using the programmed charging parameters. if t 32s .times out, the register defaults are loaded, the fault bits are set to 110, stat is pulsed high, and charging continues with default charge parameters. the fan5401 and fan5404 do not automatically initiate charging at vbus por. instead, they wait for the host to initiate charging through i 2 c commands. input current limiting to minimize charging time without overloading vbus current limitations, the ic?s input curre nt limit can be programmed by the i inlim bits (reg1[7:6]). table 7. input current limit i inlim reg1[7:6] input current limit 00 100ma 01 500ma 10 800ma 11 no limit for all versions except the fan5401 and fan5404, the otg pin establishes the input current limit when t 15min is running. for the fan5401 and fan5404, no charging occurs automatically at vbus por, so the input current limit is established by the i inlim bits. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 20 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator flow charts figure 37. charger vbus por www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 21 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator charge state yes yes disable charging indicate vbus fault no t 15min timeout? no enable i short , reset safety reg indicate charging pwm charging indicate charging no yes vbus ok? yes indicate timer fault set ce highz mode indicate charge complete no v bat < v oreg ?v rch no yes vbus ok? charge configuration state yes no disable charging indicate vbus fault no yes t 15min timeout? no i out < i term termination enabled v bat > v oreg ?v rch v bat < v short yes battery removed reset charge parameters v bat < v oreg ?v rch reset safety reg delay t int stop charging enable idet for t detect figure 38. charge mode www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 22 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator figure 39. charge configuration figure 40. hz-state www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 23 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator charge start start t 15min t 15min active? reset registers yes no start t 32sec stop t 15min i 2 c write received? yes t 15min expired? no continue charging t 32sec expired? yes no no yes timer fault : set ce ce figure 41. timer flow chart for fan5400, FAN5402, fan5403, fan5405 charge start from host control charge t 32sec expired? yes timer fault stop charging and reset registers tmr_rst bit set? reset t 32sec yes no no figure 42. timer flow chart for fan5401, fan5404 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 24 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator special charger fan5403-05 only the fan5403, fan5404, and fan5405 have additional functionality to limit input cu rrent in case a current-limited ?special charger? is supplying vbus. the fan5403-05 slowly increases the charging current until either: ? i inlim or i ocharge is reached or ? v bus =v sp . if v bus collapses to v sp when the current is ramping up, the fan5403-05 charge with an input current that keeps v bus =v sp . when the v sp control loop is limiting the charge current, the sp bit (reg5[4]) is set. table 8. v sp as function of sp bits (reg5[2:0]) sp (reg5[2:0]) dec bin hex v sp 0 000 00 4.213 1 001 01 4.293 2 010 02 4.373 3 011 03 4.453 4 100 04 4.533 5 101 05 4.613 6 110 06 4.693 7 111 07 4.773 safety settings fan5403-fan5405 only the fan5403-05 contain a safet y register (reg6) that prevents the values in oreg (reg2[7:2]) and iocharge (reg4[6:4]) from exceeding the values of the vsafe and isafe values. after v bat exceeds v short , the safety register is loaded with its default value and may be written only before any other register is written. afte r writing to any other register, the safety register is locked until v bat falls below v short . the isafe (reg6[6:4]) and vsafe (reg6[3:0]) registers establish values that limit the maximum values of i ocharge and v oreg used by the control logic. if the host attempts to write a value higher than v safe or isafe to oreg or iocharge, respectively; the vsafe, isafe value appears as the oreg, iocharge register value, respectively. table 9. i safe (i ocharge limit) as function of isafe bits (reg6[6:4]) isafe (reg6[6:4]) dec bin hex v rsense (mv) i safe (ma) 68m ? 100m ? 0 000 00 37.4 550 374 1 001 01 44.2 650 442 2 010 02 51.0 750 510 3 011 03 57.8 850 578 4 100 04 64.6 950 646 5 101 05 71.4 1050 714 6 110 06 78.2 1150 782 7 111 07 85.0 1250 850 table 10. v safe (v oreg limit) as function of vsafe bits (reg6[3:0]) vsafe (reg6[3:0]) dec bin hex max. oreg (reg2[7:2]) voreg max. 0 0000 00 100011 4.20 1 0001 00 100100 4.22 2 0010 01 100101 4.24 3 0011 02 100110 4.26 4 0100 03 100111 4.28 5 0101 04 101000 4.30 6 0110 05 101001 4.32 7 0111 06 101010 4.34 8 1000 07 101011 4.36 9 1001 08 101100 4.38 10 1010 09 101101 4.40 11 1011 0a 101110 4.42 12 1100 0b 101111 4.44 13 1101 0c 110000 4.44 14 1110 0d 110001 4.44 15 1111 0e 110010 4.44 thermal regulation and protection when the ic?s junction temperature reaches t cf (about 120c), the charger reduces its output current to 550ma to prevent overheating. if the temper ature increases beyond t shutdown ; charging is suspended, the fault bits are set to 101, and stat is pulsed high. in suspend mode, all timers stop and the state of the ic?s logic is pr eserved. charging resumes at programmed current after the die cools to about 120c. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 25 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator additional ? ja data points, measur ed using the fan540x evaluation board, are given in table 11 (measured with t a =25c). note that as power dissipation increases, the effective ? ja decreases due to the larger difference between the die temperature and its ambient. table 11. fan5400 evaluation board measured ? ja power (w) ? ja ? 0.504 54c/w 0.844 50c/w 1.506 46c/w charge mode input supply protection sleep mode when v bus falls below v bat + v slp , and v bus is above v in(min), the ic enters sleep mode to prevent the battery from draining into vbus. during sleep mode, reverse current is disabled by body switching q1. input supply low-voltage detection the ic continuously monitors vbus during charging. if v bus falls below v in(min) , the ic: 1. terminates charging 2. pulses the stat pin, sets the stat bits to 11, and sets the fault bits to 011. if v bus recovers above the v in(min) rising thresh old after time t int (about two seconds), the charging process is repeated. this function prevents the usb power bus from collapsing or oscillating when the ic is connected to a suspended usb port or a low-current-capable otg device. input over-voltage detection when the v bus exceeds vbus ovp , the ic: 1. turns off q3 2. suspends charging 3. sets the fault bits to 001, sets the stat bits to 11, and pulses the stat pin. when v bus falls about 150mv below vbus ovp , the fault is cleared and charging resumes after v bus is revalidated (see vbus por / non-compliant charger rejection) . vbus short while charging if vbus is shorted with a very low impedance while the ic is charging with i inlimit =100ma, the ic may not meet datasheet specifications until power is removed. to trigger this condition, v bus must be driven from 5v to gnd with a high slew rate. achieving this slew rate requires a 0 ? short to the usb cable less than 10cm from the connector. charge mode battery detection & protection vbat over-voltage protection the oreg voltage regulation loop prevents v bat from overshooting the oreg voltage by more than 50mv when the battery is removed. when the pwm charger runs with no battery, the te bit is not set and a battery is inserted that is charged to a voltage higher than v oreg ; pwm pulses stop. if no further pulses occur for 30ms, the ic sets the fault bits to 100, sets the stat bits to 11, and pulses the stat pin. battery detection during charging the ic can detect the presence, absence, or removal of a battery if the termination bit (te) is set. during normal charging, once v bat is close to v oreg and the termination charge current is detected, the ic terminates charging and sets the stat bits to 10. it then turns on a discharge current, i detect , for t detect . if v bat is still above v oreg ? v rch , the battery is present and the ic se ts the fault bits to 000. if v bat is below v oreg ? v rch , the battery is absent and the ic: 1. sets the registers to their default values. 2. sets the fault bits to 111. 3. resumes charging with default values after t int . battery short-circu it protection if the battery voltage is below the short-circuit threshold (v short ); a linear current source, i short , supplies v bat until v bat > v short . battery detection during power-up for fan5400 and fan5403 at vbus por, a 5k ? load is applied to vbat for 500ms to discharge any residual system capacitance in case the battery is absent. if v bat < v short , linear charging commences. when v bat rises above v short , pwm charging proceeds with the float volt age (oreg) temporarily set to 4v. if the battery voltage exceeds 3.7v within 32ms of the beginning of pwm charging, the battery is absent. if battery absent is detected: 1. high-impedance mode is entered. 2. fault bits are set to 111. 3. the t 15min timer is disabled until vbus is removed. if v bat remains below 3.7v during the initial 32ms period, the float voltage returns to the oreg register setting and pwm charging continues. system operation with no battery the FAN5402 and fan5405 continue charging after vbus por with the default param eters, regulating the v bat line to 3.54v until the host processor issues commands or the 15- minute timer expires. in this way, the FAN5402 and fan5405 can start the system without a battery. the fan540x soft-start function can interfere with the system supply with battery ab sent. the soft-start activates whenever v oreg , i inlim , or i ocharge are set from a lower to higher value. during soft-start, the i in limit drops to 100ma for about 1ms unless i inlim is set to 11 (no limit). this could cause the system processor to fail to start. to avoid this behavior, use the following sequence. 1. set the otg pin high. when vbus is plugged in, i inlim is set to 500ma until the system processor powers up and can set parameters through i 2 c. 2. program the safety register. 3. set i inlim to 11 (no limit). 4. set oreg to the desired value (typically 4.18). 5. reset the iolevel bit, then set iocharge. 6. set i inlim to 500ma if a usb source is connected. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 26 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator during the initial system star tup, while the charger ic is being programmed, the system current is limited to 325ma for 1ms during steps 4 and 5. this is the value of the soft- start i charge current used when i inlim is set to no limit. if the system is powered up without a battery present, the cv bit should be set. when a battery is inserted, the cv bit is cleared. charger status / fault status the stat pin indicates the operating condition of the ic and provides a fault indicator for interrupt driven systems. table 12. stat pin function en_stat charge state stat pin 0 x open x normal conditions open 1 charging low x fault (charging or boost) 128 ? s pulse, then open the fault bits (r0[2:0]) indicate the type of fault in charge mode (see table 13) . table 13. fault status bits during charge mode fault bit fault description b2 b1 b0 0 0 0 normal (no fault) 0 0 1 vbus ovp 0 1 0 sleep mode 0 1 1 poor input source 1 0 0 battery ovp 1 0 1 thermal shutdown 1 1 0 timer fault 1 1 1 no battery charge mode control bits setting either hz_mode or ce through i 2 c disables the charger and puts the ic into high-impedance mode and resets t 32s . if v bat < v lowv while in high-impedance mode, t 32s begins running and, when it overflows, all registers (except safety) reset, which enables t 15min charging on versions with the 15-minute timer. when t 15min overflows, the ic sets the ce bit and the ic enters high-impedance mode. if ce was set by t 15min overflow, a new charge cycle can only be initiated through i 2 c or vbus por. setting the reset bit clears all registers. if hz_mode or ce bits were set when the reset bit is set, these bits are also cleared, but the t 32s timer is not started, and the ic remains in high-impedance mode. table 14. fan5403?fan5405 disable pin and ce bit functionality charging disable pin ce hz_mode enable 0 0 0 disable x 1 x disable x x 1 disable 1 x x raising the disable pin stops t 32s from advancing, but does not reset it. if the disable pin is raised during t 15min charging, the t 15min timer is reset. operational mode control opa_mode (reg1[0]) and the hz _mode (reg1[1]) bits in conjunction with the fault state define t he operational mode of the charger. table 15. operation mode control hz_mode opa_mode fault operation mode 0 0 0 charge 0 x 1 charge configure 0 1 0 boost 1 x x high impedance the ic resets the opa_mode bit whenever the boost is deactivated, whether due to a fault or being disabled by setting the hz_mode bit. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 27 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator boost mode boost mode can be enabled if the ic is in 32-second mode with the otg pin and opa_mode bits as indicated in table 16. the otg pin active state is 1 if otg_pl=1 and 0 when otg_pl=0. if boost is active using the otg pin, boost mode is initiated even if the hz_mode=1. the hz_mode bit overrides the opa_mode bit. table 16. enabling boost otg_en otg pin hz_ mode opa_ mode boost 1 active x x enabled x x 0 1 enabled x a ctive x 0 disabled 0 x 1 x disabled 1 a ctive 1 1 disabled 0 active 0 0 disabled to remain in boost mode, the tmr_rst must be set by the host before the t 32s timer times out. if t 32s times out in boost mode; the ic resets all register s, pulses the stat pin, sets the fault bits to 110, and resets the boost bit. vbus por or reading r0 clears the fault condition. boost pwm control the ic uses a minimum on-time and computed minimum off- time to regulate vbus. the regulator achieves excellent transient response by employing current-mode modulation. this technique causes the regulator to exhibit a load line. during pwm mode, the output voltage drops slightly as the input current rises. with a constant v bat , this appears as a constant output resistance. the ?droop? caused by the output resistance when a load is applied allows the regulator to respond smoothly to load transients with no undershoot fr om the load line. this can be seen in figure 33 and figure 43. 200 225 250 275 300 325 350 2.0 2.5 3.0 3.5 4.0 4.5 5.0 battery voltage, v bat (v) output resistance (m ? ) figure 43. output resistance (r out ) v bus as a function of i load can be computed when the regulator is in pwm mode (continuous conduction) as: load out out i r 07 . 5 v ? ? ? ? ? ? ? eq. 1a at v bat =2.7v, and i load =200ma, v bus would drop to: v 005 . 5 2 . 0 327 . 0 07 . 5 v out ? ? ? ? eq. 1b pfm mode if v bus > vref boost (nominally 5.07v) when the minimum off-time has ended, the regulator enters pfm mode. boost pulses are inhibited until v bus < vref boost . the minimum on-time is increased to enable the output to pump up sufficiently with each pfm boost pulse. therefore the regulator behaves like a constant on-time regulator, with the bottom of its output voltage ri pple at 5.07v in pfm mode. table 17. boost pwm operating states mode description invoked when lin linear startup v bat > v bus ss boost soft-start v bus < v bst bst boost operating mode v bat > uvlo bst and ss completed startup when the boost regulator is shut down, current flow is prevented from v bat to v bus , as well as reverse flow from v bus to v bat . lin state when en rises, if v bat > uvlo bst , the regulator first attempts to bring pmid within 400mv of v bat using an internal 450ma current source from vbat (lin state). if pmid has not achieved v bat ? 400mv after 560 ? s, a fault state is initiated. ss state when pmid > v bat ? 400mv, the boost regulator begins switching with a reduced peak current limit of about 50% of its normal current limit. the output slews up until v bus is within 5% of its set point; at which time, the regulation loop is closed and the current limit is set to 100%. if the output fails to achieve 95% of its set point (v bst ) within 128 ? s, the current limit is incr eased to 100%. if the output fails to achieve 95% of its set point after this second 384 ? s period, a fault state is initiated. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 28 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator bst state this is the normal operating mode of the regulator. the regulator uses a minimum t off -minimum t on modulation scheme. the minimum t off is proportional to out in v v , which keeps the regulator?s switching frequency reasonably constant in ccm. t on(min) is proportional to v bat and is a higher value if the inductor current reached 0 before t off(min) in the prior cycle. to ensure the vbus does not pump significantly above the regulation point, the boost switch remains off as long as fb > v ref . boost faults if a boost fault occurs: 1. the stat pin pulses. 2. opa_mode bit is reset. 3. the power stage is in high-impedance mode. 4. the fault bits (reg0[2: 0]) are set per table 18. restart after boost faults if boost was enabled with the opa_mode bit and otg_en=0, boost mode can only be enabled through subsequent i 2 c commands since opa_mode is reset on boost faults. if otg_en=1 and the otg pin is still active (see table 16), the boost restarts after a 5.2ms delay, as shown in figure 44. if the fault condition persists, restart is attempted every 5ms until the fault clears or an i 2 c command disables the boost. table 18. fault bits during boost mode fault bit fault description b2 b1 b0 0 0 0 normal (no fault) 0 0 1 v bus > vbus ovp 0 1 0 v bus fails to achieve the voltage required to advance to the next state during soft-start or sustained (>50 ? s) current limit during the bst state. 0 1 1 v bat < uvlo bst 1 0 0 n/a: this code does not appear. 1 0 1 thermal shutdown 1 1 0 timer fault; all registers reset. 1 1 1 n/a: this code does not appear. 450ma vbus battery current 0 560 boost enabled 0 64 5200 figure 44. boost response attempting to start into v bus short circuit (times in ? s) vreg pin the vreg pin on fan5400 - FAN5402 provides a voltage protected from over-voltage su rges on vbus, which can be used to run auxiliary circuits. this voltage is essentially a current-limited replica of pm id. the maximum voltage on this node is 5.9v. fan5403-fan5405 provide a 1.8v regulated output on this pin, which can be disabled through i 2 c by setting the dis_vreg bit (reg5[6]). vreg can supply up to 2ma. this circuit, which is powered from pmid, is enabled only when pmid > v bat and does not drain current from the battery. during boost, v reg is off. it is also off when the hz_mode bit (reg1[1])=1. monitor register (reg10h) additional status monitoring bits enable the host processor to have more visibility into the status of the ic. the monitor bits are real-time status indicators and are not internally debounced or otherwise time qualified. the state of the monitor r egister bits listed in high- impedance mode are only valid when v bus is valid. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 29 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator table 19. monitor register bit definitions bit# name state active when 0 1 monitor address 10h 7 iterm_cmp v csin ? v bat < v iterm v csin ? v bat > v iterm charging with te=1 v csin ? v bat < 1mv v csin ? v bat > 1mv charging with te=0 6 vbat_cmp v bat < v short v bat > v short charging v bat < v lowv v bat > v lowv high-impedance mode v bat < uvlo bst v bat > uvlo bst boosting 5 linchg linear charging not enabled linear charging enabled charging 4 t_120 t j < 120 t j > 120 3 ichg charging current controlled by i charge control loop charging current not controlled by i charge control loop charging 2 ibus i bus limiting charging current charge current not limited by i bus charging 1 vbus_valid v bus not valid v bus is valid v bus > v bat 0 cv constant current charging c onstant voltage charging charging www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 30 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator i 2 c interface the fan540x?s serial interface is compatible with standard, fast, fast plus, and high-speed mode i 2 c-bus? specifications. the fan540x?s scl line is an input and its sda line is a bi-directional open-drain output; it can only pull down the bus when active. the sda line only pulls low during data reads and when signaling ack. all data is shifted in msb (bit 7) first. slave address table 20. i 2 c slave address byte part types 7 6 5 4 3 2 1 0 fan5400?fan5404 1 1 0 1 0 1 1 w r / fan5405 1 1 0 1 0 1 0 w r / in hex notation, the slave address assumes a 0 lsb. the hex slave address for the fan5405 is d4h and is d6h for all other parts in the family. bus timing as shown in figure 45, data is normally transferred when scl is low. data is clocked in on the rising edge of scl. typically, data transitions shortl y at or after the falling edge of scl to allow ample time for the data to set up before the next scl rising edge. scl t su t h sda data change allowed figure 45. data transfer timing each bus transaction begins and ends with sda and scl high. a transaction begins with a start condition, which is defined as sda transitioning from 1 to 0 with scl high, as shown in figure 46. scl t hd;sta sda slave address ms bit figure 46. start bit a transaction ends with a stop condition, which is defined as sda transitioning from 0 to 1 with scl high, as shown in figure 47. scl sda slave releases master drives ack(0) or nack(1) t hd;sto figure 47. stop bit during a read from the fan540x (figure 50), the master issues a repeated start after sending the register address and before resending the slave address. the repeated start is a 1-to-0 transition on sda while scl is high, as shown in figure 48. high-speed (hs) mode the protocols for high-speed (hs), low-speed (ls), and fast-speed (fs) modes are identical except the bus speed for hs mode is 3.4mhz. hs m ode is entered when the bus master sends the hs master code 00001xxx after a start condition. the master code is s ent in fast or fast plus mode (less than 1mhz clock); slaves do not ack this transmission. the master then generates a repeated start condition (figure 48) that causes all slaves on the bus to switch to hs mode. the master then sends i 2 c packets, as described above, using the hs mode clock rate and timing. the bus remains in hs mode until a stop bit (figure 47) is sent by the master. while in hs mode, packets are separated by repeated start conditions (figure 48). scl sda ack(0) or nack(1) slave releases sladdr ms bit t hd;sta t su;sta figure 48. repeated start timing www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 31 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator read and write transactions the figures below outline th e sequences for data read and write. bus control is signified by the shading of the packet, defined as master drives bus and slave drives bus . all addresses and data are msb first. table 21. bit definitions for figure 49, figure 50 symbol definition s start, see figure 46. a ack. the slave drives sda to 0 to acknowledge the preceding packet. a nack. the slave sends a 1 to nack the preceding packet. r repeated start, see figure 48 p stop, see figure 47 s slave address a reg addr a a p 0 7 bits 8 bits 8 bits data 000 figure 49. write transaction s slave address a reg addr a 0 7 bits 8 bits r slave address 7 bits 1 a data a 8 bits 00 01 p figure 50. read transaction www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 32 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator register descriptions the fan5400-FAN5402 have seven user-accessible registers; the fa n5403-05 have an additional two registers, as defined in table 22. table 22. i 2 c register address ic register address bits name reg# 7 6 5 4 3 2 1 0 all control0 0 0 0 0 0 0 0 0 0 control1 1 0 0 0 0 0 0 0 1 oreg 2 0 0 0 0 0 0 1 0 ic_info 03 or 3bh 0 0 0 0 0 0 1 1 ibat 4 0 0 0 0 0 1 0 0 fan5403-fan5405 sp_charger 5 0 0 0 0 0 1 0 1 safety 6 0 0 0 0 0 1 1 0 all monitor 10h 0 0 0 0 1 0 1 0 table 23. register bit definitions this table defines the operation of each register bit for all ic versions. default values are in bold text. bit name value type description control0 register address: 00 default value=x1xx 0xxx 7 tmr_rst otg 1 w writing a 1 resets the t 32s timer; writing a 0 has no effect r returns the otg pin level (1=high) 6 en_stat 0 r/w prevents stat pin from going low duri ng charging; stat pin still pulses to enunciate faults 1 enables stat pin low when ic is charging 5:4 stat 00 r ready 01 charge in progress 10 charge done 11 fault 3 boost 0 r ic is not in boost mode 1 ic is in boost mode 2:0 fault r fault status bits: for charge mode, see table 13; for boost mode: see table 18 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 33 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator table 23. register bit definitions (continued) bit name value type description control1 register address: 01 default value=0011 0000 (30h) 7:6 i inlim r/w input current limit, see table 7 5:4 v lowv 00 r/w 3.4v weak battery voltage threshold 01 3.5v 10 3.6v 11 3.7v 3 te 0 r/w disable charge current termination 1 enable charge current termination 2 ce 0 r/w charger enabled 1 charger disabled 1 hz_mode 0 r/w not high-impedance mode see table 16 1 high-impedance mode 0 opa_mode 0 r/w charge mode 1 boost mode oreg register address: 02 default value=0000 1010 (0ah) 7:2 oreg r/w charger output ?float? voltage; program mable from 3.5 to 4.44v in 20mv increments; defaults to 000010 (3.54v) , see table 3 1 otg_pl 0 r/w otg pin active low 1 otg pin active high 0 otg_en 0 r/w disables otg pin 1 enables otg pin ic_info register address: 03 or 3b default value=100x xxxx 7:5 vendor code 100 r identifies fairchild semiconductor as the ic supplier 4:3 pn r part number bits, see the ordering info on page 1 2:0 rev r ic revision, revision 1.x, wher e x is the decimal of these three bits ibat register address: 04 default value=1000 1001 (89h) 7 reset 1 w writing a 1 resets charge parameters, except the safety register (reg6), to their defaults: writing a 0 has no effect; read returns 1 6:4 iocharge table 5 r/w program s the maximum charge current, see table 5 3 reserved 1 r unused 2:0 iterm table 6 r/w sets the curre nt used for charging termination, see table 6 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 34 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator table 23. register bit definitions (continued) sp_charger (fan5403 ? fan5405) register address: 05 default value=001x x100 7 reserved 0 r unused 6 dis_vreg 0 r/w 1.8v regulator is on 1 1.8v regulator is off 5 io_level 0 r/w output current is c ontrolled by iocharge bits 1 voltage across r sense for output current control is set to 22.1mv (325ma for r sense =68m ? , 221ma for 100m ? ) 4 sp 0 r special charger is not active (v bus is able to stay above v sp ) 1 special charger has been detected and v bus is being regulated to v sp 3 en_level 0 r disable pin is low 1 disable pin is high 2:0 vsp table 8 r/w special char ger input regulation voltage, see table 8 safety (fan5403 ? fan5405) register address: 06 default value=0100 0000 (40h) 7 reserved 0 r bit disabled and always returns 0 when read back 6:4 isafe table 9 r/w sets the maximum i ocharge value used by the control circuit, see table 9 3:0 vsafe table 10 r/w sets the maximum v oreg used by the control circuit, see table 10 monitor register address: 10h (16) see table 19 7 iterm_cmp see table 19 r iterm comparator output, 1 when vrsense > iterm reference 6 vbat_cmp r output of vbat comparator 5 linchg r 30ma linear charger on 4 t_120 r thermal regulation comparator; when=1 an d t_145=0, the charge current is limited to 22.1mv across r sense 3 ichg r 0 indicates the i charge loop is controlling the battery charge current 2 ibus r 0 indicates the i bus (input current) loop is controlling the battery charge current 1 vbus_valid r 1 indicates v bus has passed validation and is capable of charging 0 cv r 1 indicates the constant-voltage loop (o reg) is controlling the charger and all current limiting loops have released www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 35 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator pcb layout recommendations bypass capacitors should be placed as close to the ic as possible. in particular, the total loop length for cmid should be minimized to reduce overshoot and ringing on the sw, pmid, and vbus pins. all power and ground pins must be routed to their bypass capacitors using top copper if possible. copper area connecting to the ic should be maximized to improve thermal performance. figure 51. pcb layout recommendations www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 36 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator physical dimensions bottom view side views top view ball a1 index area 1 2 3 4 a b c d e seating plane 20x a1 c 0.005 cab f ?0.2600.02 e d b a 0.625 0.547 0.06 c 0.05 c e d f 0.3780.018 0.2080.021 notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerance per asmey14.5m, 1994. d. datum c is defined by the spherical crowns of the balls. e. package nominal height is 586 microns 39 microns (547-625 microns). f. for dimensions d, e, x, and y see product datasheet. g. drawing filnam e: mkt-uc020aarev2. 0.03 c 2x 0.03 c 2x 0.40 1.20 0.40 1.60 (y) 0.018 (x) 0.018 recommended land pattern (nsmd type) ?0.20 cu pad ?0.30 solder mask opening 0.40 1.20 0.40 1.60 figure 52. 20-ball wlcsp, 4x5 array, 0.4mm pitch, 250m ball product-specific dimensions product d e x y fan540xucx 1.960 + 0.030 1.870 + 0.030 0.335 0.180 package drawings are provided as a service to customers considering fairchild component s. drawings may change in any manner wit hout notice. please note the revision and/or date on the drawing and contact a fairchild semi conductor representative to verify or o btain the most recent revision. package specific ations do not expand the terms of fairchild?s worldwide terms and conditi ons, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan5400 family ? rev. 1.0.7 37 fan5400 family ? usb-compliant si ngle-cell li-ion switching charge r with usb-otg boost regulator www.datasheet.co.kr datasheet pdf - http://www..net/

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